module Core(
  input         clock,
  input         reset,
  output [31:0] io_imem_addr,
  input  [31:0] io_imem_inst,
  output        io_exit
);

  reg [31:0] pc_reg; // @[Core.scala 24:23]
  wire [31:0] _pc_reg_T_1 = pc_reg + 32'h4; // @[Core.scala 25:20]
  wire  _T_1 = ~reset; // @[Core.scala 39:9]

  assign io_imem_addr = pc_reg; // @[Core.scala 29:16]
  assign io_exit = io_imem_inst == 32'h5; // @[Core.scala 38:20]

  always @(posedge clock) begin
    if (reset) begin // @[Core.scala 24:23]
      pc_reg <= 32'h0; // @[Core.scala 24:23]
    end else begin
      pc_reg <= _pc_reg_T_1; // @[Core.scala 25:10]
    end

endmodule
